Electrically Erasable Programmable Read-Only Memory (EEPROM) memory units are popularly adapted to the information electronics. With the advancing technique, the faster EEPROM so-called flash memory has been developed recently to overcome the lower erasing speed, larger area per cell and higher cost of the conventional EEPROM. Basically, a typical EEPROM is formed by a floating gate transistor. During the mode of writing data, a high voltage is applied to a control gate so that the electrons transverses from the drain region into the floating gate through the tunneling oxide layer by the Fowler-Nordheim tunneling effect to increase the threshold voltage. During the mode of erasing data, a high voltage is applied to the source region so that the prior electrons injected into the floating gate flows into the source region or substrate through the tunneling oxide layer to recover original threshold voltage.
In the recent decade, a main object of the development is to consider how to achieve the purpose of efficiently rewriting and erasing a data stored in the flash memory by charging or discharging electrons. Furthermore, higher capacity and lower power consumption are also the goal of the industry at present. The cell is typically the unit of the flash memory. The flash memory is not only characterized with reading, writing capability, but also erasing a sector or page, simultaneously. Therefore, the advantages of the flash memory include the higher reading speed, higher density and lower cost. The flash memory has become a considerably significant device in semiconductor industry.
Please refer to FIG. 1a, where it shows a cross sectional view of a semiconductor wafer illustrating the programming mode of flash memory according to the prior art. During the mode of programming data according to the prior art, a high voltage is applied to a control gate 105 so that the hot carriers are driven from a source region 101a in a silicon substrate 101 into a floating gate 103 through a gate oxide layer 102.
FIG. 1b is a cross sectional view of a semiconductor wafer illustrating the erasing mode of flash memory according to the prior art. During the mode of erasing data, a low voltage or ground potential is applied to the control gate 105 while a high voltage is applied to the silicon substrate 101, thereby driving the electrons from the floating gate 103 into the aforementioned source region 101a through the gate oxide layer 102.
As mentioned above, in the prior art, a set of data can be programmed or erased at one time. The number of the memory units in the flash memory means the number of cells that can be programmed or erased. If there are two sectors that store the data in a single cell, respectively, the device may program or erase two sets of data. Therefore, the capacity of the data set that is programmed or erased by the flash device is twice of the number of the traditional memory units in the flash memory.